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High-Performance Computing
Multi-Chip Packaging Electrical Compensation Technology for Panel-Level Interposer
- Features
- Die Shift Compensation XY：50 μm；θ：0.3°
- Chip Number：4 Chips
- Panel Per Hour：16 @G2.5
- RDL Stacking：4 Layers
- Line/Via：3μm/6μm
- Warpage：< 0.5mm @G2.5 (After Debonding)
Description
According to the high-performance computing needs of future ICs, a large size module is a trend to integrate more chips. Maskless high-resolution digital dynamic connection technology is developed and verified in the Re-distribution Layer (RDL) of chip first IC packaging, achieving a compensation capability for horizontal displacement (XY) of 50μm and angular displacement (θ) of 0.3 degrees. It also features circuit electrical characteristic compensation design, making it suitable for panel-level interposer applications.| Items | 2024 | 2023 |
|---|---|---|
| Electrical Compensation Design | Resolution: 2μm | NA |
| Digital Dynamic Connection | XY:50μm; θ: 0.3° | XY:50μm; θ: 0.3° |
| Low Temp. Build up Film with High Resolution | Line/Via: 3μm/6μm; Curing: 180°C | Line/Via: 5μm/7μm; Curing: 180°C |
Dept：Electronic and Optoelectronic System Research Laboratories
POC：吳胤璟
Tel：03-5913685
E-mail：gary.wu@itri.org.tw